My guess is that they would be the same, but I can't say with 100% certainty that they (since I own only american retail and no japanese carts :/)Just wondering, is there a chance timing is different in Japanese carts? I may want to try it in my Japanese LeafGreen cartridge.
I've tested both and the results are mostly the same (some seeds are easier to hit than others and vice versa). I think this is because the ds clock moves at double the speed of the gba clock (or whatever, arm7 cpu), so hitting the same seeds for both shouldn't be a problem.they're all exactly the same. if it's different it's a result of your gba acting strangely. or if you're using a ds you'll get different results too. timer1 runs at 16.78mhz on a gba and 33.something mhz on a ds.
e: the F(system clock) that timer1 runs against is the speed of the arm7 cpu in both cases. so.. that's why it's different. it's moving at the speed of the cpu.
does inputting the necessary criteria in pokerng old version then transferring the seed results along with the nature and ivs on rngreporter work? if not, idk.How do I quickly find my seed from the information I have about the Pokemon I caught?
The FRLGSeedFinder requires me to type in a Seed. So I am confused.
Not exactly, the whole "Noisy" phenomenon is the Method H at work, essentially Method K.I don't think sweet scenting to check your seed before hitting your target frame will work.
While you're sweet scenting, several frames are skipped, and then the game enters noisy mode when you enter a battle. So using this method to check your seed before a long wait is unfeasible.
Zari picked a small enough frame so that he wouldn't have to check his seed before battling Mewtwo, so he probably didn't run into this problem.
no it's not at all. pid restrictions don't cause the rng to advance 2 at a time when in battle/not doing anything but walking around.Not exactly, the whole "Noisy" phenomenon is the Method H at work, essentially Method K.
It's problematic to trace back to what frame you had originally hit, but with enough work it's possible.
Now, from looking over the code, we can conclude that even though Gamefreak ignored ARM's advice and used modulus anyway, they didn't take precautions to keep the code up to speed. They also likely didn't use those library functions that would make 32-bit division only 20-140 cycles. Their mod function uses(on average) 270 instructions to do PID % 0x19. If you follow the routine out and watch the number of cycles used, it comes out to roughly 750(!!) on average.The ARM instruction set does not provide integer division. Divisions are typically
implemented by calling a C-library function (__rt_sdiv for signed and __rt_udiv for
unsigned division). Depending on the numerator and denominator, a 32-bit division takes
20-140 cycles. The division function takes a constant time plus a time for each bit to
divide:
Time(numerator / denominator)
= C0 + C1 * log2(numerator / denominator) =
= C0 + C1 * (log2(numerator) - log2(denominator)).
The current version takes about 20 + 4.3N cycles.
As division is an expensive operation, it is desirable to avoid it where possible. Sometimes
expressions can be rewritten so that a division becomes a multiplication. For example,
(x / y) > z can be rewritten as x > (z * y) if it is known that y is positive and y * z
fits in an integer.
It is best to use unsigned division by ensuring that one of the operands is unsigned, as this
is faster than signed division. This applies both to the division subroutines and to divisions
by a power of two (see 3.2 Division and remainder by powers of two).
082E7BE0 2900 cmp r1,#0x0
082E7BE2 D058 beq #0x82E7C96
082E7BE4 2301 mov r3,#0x1
082E7BE6 4288 cmp r0,r1
082E7BE8 D200 bcs #0x82E7BEC
082E7BEA 46F7 mov r15,r14
082E7BEC B410 push {r4}
082E7BEE 2401 mov r4,#0x1
082E7BF0 0724 lsl r4,r4,#0x1C
082E7BF2 42A1 cmp r1,r4
082E7BF4 D204 bcs #0x82E7C00
082E7BF6 4281 cmp r1,r0
082E7BF8 D202 bcs #0x82E7C00
082E7BFA 0109 lsl r1,r1,#0x4
082E7BFC 011B lsl r3,r3,#0x4
082E7BFE E7F8 b #0x82E7BF2
082E7C00 00E4 lsl r4,r4,#0x3
082E7C02 42A1 cmp r1,r4
082E7C04 D204 bcs #0x82E7C10
082E7C06 4281 cmp r1,r0
082E7C08 D202 bcs #0x82E7C10
082E7C0A 0049 lsl r1,r1,#0x1
082E7C0C 005B lsl r3,r3,#0x1
082E7C0E E7F8 b #0x82E7C02
082E7C10 2200 mov r2,#0x0
082E7C12 4288 cmp r0,r1
082E7C14 D300 bcc #0x82E7C18
082E7C16 1A40 sub r0,r0,r1
082E7C18 084C lsr r4,r1,#0x1
082E7C1A 42A0 cmp r0,r4
082E7C1C D305 bcc #0x82E7C2A
082E7C1E 1B00 sub r0,r0,r4
082E7C20 469C mov r12,r3
082E7C22 2401 mov r4,#0x1
082E7C24 41E3 ror r3,r4
082E7C26 431A orr r2,r3
082E7C28 4663 mov r3,r12
082E7C2A 088C lsr r4,r1,#0x2
082E7C2C 42A0 cmp r0,r4
082E7C2E D305 bcc #0x82E7C3C
082E7C30 1B00 sub r0,r0,r4
082E7C32 469C mov r12,r3
082E7C34 2402 mov r4,#0x2
082E7C36 41E3 ror r3,r4
082E7C38 431A orr r2,r3
082E7C3A 4663 mov r3,r12
082E7C3C 08CC lsr r4,r1,#0x3
082E7C3E 42A0 cmp r0,r4
082E7C40 D305 bcc #0x82E7C4E
082E7C42 1B00 sub r0,r0,r4
082E7C44 469C mov r12,r3
082E7C46 2403 mov r4,#0x3
082E7C48 41E3 ror r3,r4
082E7C4A 431A orr r2,r3
082E7C4C 4663 mov r3,r12
082E7C4E 469C mov r12,r3
082E7C50 2800 cmp r0,#0x0
082E7C52 D003 beq #0x82E7C5C
082E7C54 091B lsr r3,r3,#0x4
082E7C56 D001 beq #0x82E7C5C
082E7C58 0909 lsr r1,r1,#0x4
082E7C5A E7D9 b #0x82E7C10
082E7C5C 240E mov r4,#0xE
082E7C5E 0724 lsl r4,r4,#0x1C
082E7C60 4022 and r2,r4
082E7C62 D101 bne #0x82E7C68
082E7C64 BC10 pop {r4}
082E7C66 46F7 mov r15,r14
:0209C2C8 E3510000 cmp r1,#0x0
:0209C2CC 012FFF1E bxeq r14
:0209C2D0 E1500001 cmp r0,r1
:0209C2D4 31A01000 movcc r1,r0
:0209C2D8 33A00000 movcc r0,#0x0
:0209C2DC 312FFF1E bxcc r14
:0209C2E0 E3A0201C mov r2,#0x1C
:0209C2E4 E1A03220 mov r3,r0,lsr #0x4
:0209C2E8 E1510623 cmp r1,r3,lsr #0xc
:0209C2EC D2422010 suble r2,r2,#0x10
:0209C2F0 D1A03823 movle r3,r3,lsr #0x10
:0209C2F4 E1510223 cmp r1,r3,lsr #0x4
:0209C2F8 D2422008 suble r2,r2,#0x8
:0209C2FC D1A03423 movle r3,r3,lsr #0x8
:0209C300 E1510003 cmp r1,r3
:0209C304 D2422004 suble r2,r2,#0x4
:0209C308 D1A03223 movle r3,r3,lsr #0x4
:0209C30C E1A00210 mov r0,r0,lsl r2
:0209C310 E2611000 rsb r1,r1,#0x0
:0209C314 E0900000 adds r0,r0,r0
:0209C318 E0822082 add r2,r2,r2,lsl #0x1
:0209C31C E08FF102 add r15,r15,r2,lsl #0x2
:0209C320 E1A00000 nop(mov r0,r0)mov r0,r0
:0209C324 E0B13083 adcs r3,r1,r3,lsl #0x1
:0209C328 30433001 subcc r3,r3,r1
:0209C32C E0B00000 adcs r0,r0,r0
:0209C330 E0B13083 adcs r3,r1,r3,lsl #0x1
:0209C334 30433001 subcc r3,r3,r1
:0209C338 E0B00000 adcs r0,r0,r0
:0209C33C E0B13083 adcs r3,r1,r3,lsl #0x1
:0209C340 30433001 subcc r3,r3,r1
:0209C344 E0B00000 adcs r0,r0,r0
:0209C348 E0B13083 adcs r3,r1,r3,lsl #0x1
:0209C34C 30433001 subcc r3,r3,r1
:0209C350 E0B00000 adcs r0,r0,r0
:0209C354 E0B13083 adcs r3,r1,r3,lsl #0x1
:0209C358 30433001 subcc r3,r3,r1
:0209C35C E0B00000 adcs r0,r0,r0
:0209C360 E0B13083 adcs r3,r1,r3,lsl #0x1
:0209C364 30433001 subcc r3,r3,r1
:0209C368 E0B00000 adcs r0,r0,r0
:0209C36C E0B13083 adcs r3,r1,r3,lsl #0x1
:0209C370 30433001 subcc r3,r3,r1
:0209C374 E0B00000 adcs r0,r0,r0
:0209C378 E0B13083 adcs r3,r1,r3,lsl #0x1
:0209C37C 30433001 subcc r3,r3,r1
:0209C380 E0B00000 adcs r0,r0,r0
:0209C384 E0B13083 adcs r3,r1,r3,lsl #0x1
:0209C388 30433001 subcc r3,r3,r1
:0209C38C E0B00000 adcs r0,r0,r0
:0209C390 E0B13083 adcs r3,r1,r3,lsl #0x1
:0209C394 30433001 subcc r3,r3,r1
:0209C398 E0B00000 adcs r0,r0,r0
:0209C39C E0B13083 adcs r3,r1,r3,lsl #0x1
:0209C3A0 30433001 subcc r3,r3,r1
:0209C3A4 E0B00000 adcs r0,r0,r0
:0209C3A8 E0B13083 adcs r3,r1,r3,lsl #0x1
:0209C3AC 30433001 subcc r3,r3,r1
:0209C3B0 E0B00000 adcs r0,r0,r0
:0209C3B4 E0B13083 adcs r3,r1,r3,lsl #0x1
:0209C3B8 30433001 subcc r3,r3,r1
:0209C3BC E0B00000 adcs r0,r0,r0
:0209C3C0 E0B13083 adcs r3,r1,r3,lsl #0x1
:0209C3C4 30433001 subcc r3,r3,r1
:0209C3C8 E0B00000 adcs r0,r0,r0
:0209C3CC E0B13083 adcs r3,r1,r3,lsl #0x1
:0209C3D0 30433001 subcc r3,r3,r1
:0209C3D4 E0B00000 adcs r0,r0,r0
:0209C3D8 E0B13083 adcs r3,r1,r3,lsl #0x1
:0209C3DC 30433001 subcc r3,r3,r1
:0209C3E0 E0B00000 adcs r0,r0,r0
:0209C3E4 E0B13083 adcs r3,r1,r3,lsl #0x1
:0209C3E8 30433001 subcc r3,r3,r1
:0209C3EC E0B00000 adcs r0,r0,r0
:0209C3F0 E0B13083 adcs r3,r1,r3,lsl #0x1
:0209C3F4 30433001 subcc r3,r3,r1
:0209C3F8 E0B00000 adcs r0,r0,r0
:0209C3FC E0B13083 adcs r3,r1,r3,lsl #0x1
:0209C400 30433001 subcc r3,r3,r1
:0209C404 E0B00000 adcs r0,r0,r0
:0209C408 E0B13083 adcs r3,r1,r3,lsl #0x1
:0209C40C 30433001 subcc r3,r3,r1
:0209C410 E0B00000 adcs r0,r0,r0
:0209C414 E0B13083 adcs r3,r1,r3,lsl #0x1
:0209C418 30433001 subcc r3,r3,r1
:0209C41C E0B00000 adcs r0,r0,r0
:0209C420 E0B13083 adcs r3,r1,r3,lsl #0x1
:0209C424 30433001 subcc r3,r3,r1
:0209C428 E0B00000 adcs r0,r0,r0
:0209C42C E0B13083 adcs r3,r1,r3,lsl #0x1
:0209C430 30433001 subcc r3,r3,r1
:0209C434 E0B00000 adcs r0,r0,r0
:0209C438 E0B13083 adcs r3,r1,r3,lsl #0x1
:0209C43C 30433001 subcc r3,r3,r1
:0209C440 E0B00000 adcs r0,r0,r0
:0209C444 E0B13083 adcs r3,r1,r3,lsl #0x1
:0209C448 30433001 subcc r3,r3,r1
:0209C44C E0B00000 adcs r0,r0,r0
:0209C450 E0B13083 adcs r3,r1,r3,lsl #0x1
:0209C454 30433001 subcc r3,r3,r1
:0209C458 E0B00000 adcs r0,r0,r0
:0209C45C E0B13083 adcs r3,r1,r3,lsl #0x1
:0209C460 30433001 subcc r3,r3,r1
:0209C464 E0B00000 adcs r0,r0,r0
:0209C468 E0B13083 adcs r3,r1,r3,lsl #0x1
:0209C46C 30433001 subcc r3,r3,r1
:0209C470 E0B00000 adcs r0,r0,r0
:0209C474 E0B13083 adcs r3,r1,r3,lsl #0x1
:0209C478 30433001 subcc r3,r3,r1
:0209C47C E0B00000 adcs r0,r0,r0
:0209C480 E0B13083 adcs r3,r1,r3,lsl #0x1
:0209C484 30433001 subcc r3,r3,r1
:0209C488 E0B00000 adcs r0,r0,r0
:0209C48C E0B13083 adcs r3,r1,r3,lsl #0x1
:0209C490 30433001 subcc r3,r3,r1
:0209C494 E0B00000 adcs r0,r0,r0
:0209C498 E0B13083 adcs r3,r1,r3,lsl #0x1
:0209C49C 30433001 subcc r3,r3,r1
:0209C4A0 E0B00000 adcs r0,r0,r0
:0209C4A4 E1A01003 mov r1,r3
:0209C4A8 E12FFF1E bx r14
and while i'm thinking of it, those times when the rng seems to be skipping a seed, it actually isn't. the rng is doing 2 worthless advancements per frame instead of 1 at those times. some genius at gamefreak thought that adding another worthless rand() call at the top of a different function was a great idea.
can someone name a place where the rng advances double-time outside of battle? i'd like to see if it's the same for that and (preferably) what exactly causes it.
Well, they got something really freakin' random alright, but not in the way they intended. :)i should also probably mention that those walls of text above are also responsible for split breeding spreads.
also, the pokemon gba games were gamefreak's first foray into arm/programming for the arm cpu series, so i guess it's sort of understandable that it didn't come out great?
#include <nds.h>
#include <stdio.h>
#include <timers.h>
#define REG_GXSTAT (*(vu32*)0x04000600)
#define REG_T0 (*(vu16*)0x04000100)
#define REG_T1 (*(vu16*)0x04000104)
#define REG_T2 (*(vu16*)0x04000108)
#define REG_T3 (*(vu16*)0x0400010C)
volatile int frame = 0;
typedef unsigned short u16_t;
typedef unsigned int u32_t;
typedef unsigned long long u64_t;
u32_t rand64();
u64_t mul64(u64_t num1, u64_t num2);
u16_t rand32();
u64_t seed = 0;
u32_t seed32 = 0;
[b][i]
//---------------------------------------------------------------------------------
void Vblank() {
//---------------------------------------------------------------------------------
frame++;
rand32();
rand64();
}
[/b][/i]
//---------------------------------------------------------------------------------
int main(void) {
//---------------------------------------------------------------------------------
lcdSwap();
irqSet(IRQ_VBLANK, Vblank);
consoleDemoInit();
int i = rand() % 4;
switch(i)
{
case 0:
TIMER_CR(0) = TIMER_ENABLE | TIMER_DIV_1;
break;
case 1:
TIMER_CR(1) = TIMER_ENABLE | TIMER_DIV_64;
break;
case 2:
TIMER_CR(2) = TIMER_ENABLE | TIMER_DIV_256;
break;
case 3:
TIMER_CR(3) = TIMER_ENABLE | TIMER_DIV_1024;
}
iprintf(" Test\n\n");
//iprintf(" %X \n", t0);
u32_t gx = REG_GXSTAT + rand();
seed = (u64_t)gx;
while(1) {
//timerStop(i);
u16_t lc32 = rand32();
u32_t lc64 = rand64();
iprintf("\x1b[10;0HFrame: %u", frame);
iprintf("\x1b[12;0H64-bit: %16llX", seed);
iprintf("\x1b[14;0H64-bit return: %08X", lc64);
iprintf("\x1b[16;0H32-bit: %08X", seed32);
iprintf("\x1b[18;0H32-bit return: %04X", lc32);
swiWaitForVBlank();
}
return 0;
}
u32_t rand64()
{
const u64_t a = 0x5d588b656c078965;
const u64_t c = 0x0000000000269ec3;
seed = mul64(seed, a) + c;
return (u32_t)(seed >> 32);
}
u64_t mul64(u64_t num1, u64_t num2)
{
u64_t result = (num1 * num2);
return result;
}
u16_t rand32()
{
const u32_t a = 0x41C64E6D;
const u32_t c = 0x00006073;
seed32 = (a * seed32) + c;
return (u16_t)(seed32 >> 16);
}